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Ordering number : EN 4873
Thick Film Hybrid IC
STK6217
Unidirectional DC Motor Driver with Constant-Speed Digital Servo Controller (output current: 8 A)
Overview
The STK6217 is a hybrid IC that combines in a single package a unidirectional DC motor driver, a PLL constant-speed controller (the LC7991) and associated peripheral components, including a separately excited oscillator, a comparator, and an FG amplifier. The motor controller uses a PLL circuit for precise motor control. The wide range of the STK6217's FG lock frequency allows it to handle a wide range of applications. Since the motor driver block uses MOSFET devices as power elements, it features high output currents (rush current) and low loss.
* Speed lock indicator output directly drives an external LED. * TTL level compatible ROT input * MOSFET power elements provide high output currents (rush current). * Low-loss PWM speed controller (built-in externally excited oscillator: 25 kHz) * Wide power supply voltage range (VDSS = 60 V) * Built-in motor start-up overcurrent limiter function
Package Dimensions
unit: mm 4138
[STK6217]
Applications
* Plain paper copier DC motor drivers * FAX paper transport motor drivers * Other DC motor applications
Features
* High FG frequency upper limit (locking range: 200 to 2500 Hz) * Built-in FG divider (FG lock upper limit with divider in use: 5000 Hz)
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage 1 Maximum supply voltage 2 Maximum motor rush current Maximum input voltage Storage temperature range Junction temperature Operating substrate temperature Symbol VCC1 max VCC2 max VIH max Tstg Tj max Tc max No signal No signal Conditions Ratings 52 7 18 7 -40 to +125 150 105 Unit V V A V C C C
IO peak max Duty 1%, period 100 ms
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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N2894TH (OT) No. 4873-1/12
STK6217
Allowable Operating Ranges at Ta = 25C
Parameter Operating supply voltage 1 Operating supply voltage 2 Motor output current FET withstand voltage Input voltage Symbol VCC1 VCC2 IO VDSS VIH Input active Input active DC (Tc = 25C) Conditions Ratings 10 to 42 5 5% 8 60 min VCC2 Unit V V A V V
Operating Characteristics at Ta = 25C, VCC1 = 24 V, VCC2 = 5.0 V
Ratings Parameter VCC2 current dissipation Output FET saturation voltage Built-in oscillator frequency OSC output amplitude OSC output effective amplitude Common mode input voltage range FG amplifier feedback resistance High input level voltage Low input level voltage High input level current Low input level current High output level current Low output level current Input frequency range Symbol ICC VSAT fO VOP-P Vorms VICM Rf VIH VIL IIH IIL IOH IOL fXI fFG FG lock frequency Output cut voltage fFLOCK fFLOCK Vocut Lock input VOH = VCC2 - 0.4 V Lock input VOL = 0.4 V XI input FGI input FG input divider off FG input divider on Pin 5 input voltage 200 400 0 2 0.1 10.5 50 2500 5000 25 DIV1 to DIV3, PR1 and PR2 inputs -1 -2 DIV1 to DIV3, PR1, PR2 and ROT inputs Pin 7 output voltage Integrating amplifier and FG amplifier input voltage Conditions When the ROT input is used RL = 3 21 1.9 0.54 0 95 0.7 VCC2 0 100 min typ 10 0.95 25 2.3 0.66 max 15 1.3 31 2.7 0.80 VCC2 - 1.5 105 VCC2 0.3 VCC2 1 Unit mA V kHz Vp-p Vrms V k V V A A mA mA MHz kHz Hz Hz mV
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Vref4 VCC2 Vref1 Vref2 Vref3 FG Rf Mix in Mix out XI XO DIV1 DIV2 DIV3 PR1 PR2 ROT Lock SG Motor rotate/stop input; H: stop, L: rotate Lock output; Outputs a low level when locked Ground Phase comparison range select Variable divider setting Motor start-up current control reference voltage Power supply voltage input (+5 V) H/IC built-in oscillator bias voltage setting Integrating amplifier reference voltage setting FG input reference voltage setting FG input Integrating amplifier output Integrating amplifier input PO and FO sum output (PO and FO each have a 100 k output resistance.) Crystal oscillator connection (input) Crystal oscillator connection (output) Vrs Current detection resistor connection Symbol OUT Motor output Function
No. 4873-2/12
STK6217
I/O Formats
Pin No. Format
16, 17, 18, 19
14, 15
21
22
13
No. 4873-3/12
STK6217
Equivalent Circuit
Unit (resistance: , capacitance: F)
Sample Application Circuit
Unit (resistance: , capacitance: F)
The circuit shown above locks at an FG frequency of 2000 Hz. Reference frequency: 8.2 MHz Variable divider: 1/2 FG divider: Off
No. 4873-4/12
STK6217
Operating Principles
1. Overview Figure 1 shows the block diagram for the STK6217. The PLL control block compares the frequencies and phases of the FG signal frequency fed back from the motor with a reference clock, which is formed by dividing a reference signal. When they agree, the frequency is locked with a 50% duty. The control signals consist of two systems with D/A converted outputs: FO, which is the frequency control output and PO, which is the phase control output. Since PLL control provides a motor speed that is synchronized with a reference clock frequency fref, which is created by dividing a reference signal, the stability of fref directly influences the stability of the rotation. Therefore, quartz precision digital control is possible by using a crystal oscillator for reference signal generation. The control signals are added by an integration circuit, which also functions as an active filter. It is here that the servo system gain and phase compensation are performed. The output of this system is sent to the PWM conversion block and a PWM signal, which is based on the period of an associated oscillator circuit, is input to the unidirectional driver of the final stage, which drives the DC motor. 2. Motor Speed, Resonant Frequency, and Encoder Pulse Count The frequency fFG of the signal generated by the encoder is given by: fFG (Hz) = N (rpm) x P (P/R) ......................................................................................... x 60
Where, N: Motor speed (rpm) P: Number of pulses per encoder rotation Formula x can be transformed as follows: N (rpm) = 60 x fFG ........................................................................................................ y P (P/R)
Alternatively, P (P/R) = 60 x fFG ........................................................................................................ z N
Here, the relationship with the oscillator resonant frequency is given by: N (rpm) = 60 P x fxtal .......................................................................... { DIV x 2050 (1025)
Alternatively, P (P/R) = 60 N x fxtal .......................................................................... | DIV x 2050 (1025)
Here, DIV: Variable divider ratio See item 3-1, subsection (3). The value (1025) is used when the fFG input frequency is divided by 2 (as determined by DIV setting). See item 3-1, subsection (3). Note that the following three methods for increasing the stability of the motor speed can be considered.
x y z
Increasing the number of encoder output pulses for a given motor speed. Not using the FG divider if at all possible, since using it decreases the precision of the rotation data. Setting the divider ratio to as low a value as possible, so that the oscillator precision is not reduced.
No. 4873-5/12
STK6217
Figure 1 STK6217 Block Diagram
Figure 2 PLL IC Block Diagram
No. 4873-6/12
STK6217 3. Block Functional Descriptions 3-1 Reference Signal Generation Block (1) Crystal oscillator circuit The controller block generates a reference clock using a crystal oscillator and a capacitor connected to the XI and XO pins. It is also possible to leave the XO pin open and input an external clock to the XI pin.
Reference oscillator calculation External clock input
The external clock should be a square wave with an amplitude of 5 V and a duty of approximately 50%. VDD = 5 V.
(2) Crystal resonant frequency calculation After determining the FG frequency to be locked, use the following formula to derive the required crystal frequency. a) With the FG divider off fxtal = fFGLock x DIV x 2050 (Hz) b) With the FG divider on fxtal = fFGLock x DIV x 1025 (Hz) Where: fxtal: Crystal resonant frequency fFGLock: The FG frequency to be locked DIV: The variable divider ratio (3) Variable divider and the FG divider The controller block includes a 6-setting variable divider and an FG divider (divide-by-2, by-passable) to expand the range of input FG frequencies. These dividers are controlled by the three pins DIV1, DIV2 and DIV3 as shown in Table 1. Table 1 Divider Control
Control input DIV3 High level High level High level High level Low level Low level Low level Low level DIV2 High level High level Low level Low level High level High level Low level Low level DIV1 High level Low level High level Low level High level Low level High level Low level Variable divider ratio 20 10 6 3 2 1 2 1 FG divider OFF OFF OFF OFF OFF OFF ON ON
No. 4873-7/12
STK6217 3-2 Servo Control Block The servo block compares the reference clock generated by the reference signal generation block with the FGI input (the FG signal input from the motor) and generates three output signals: FO (frequency system control output), PO (phase system control output), and Lock (the lock indicator output). The FO and PO outputs are 8-bit D/A converter outputs. The motor drive signal is created from these two outputs. The Lock output indicates whether the motor is within the lock range. (1) Servo Operation Control system operation is divided into the following three aspects depending on the input FG frequency: drive, tracking (locked), and brake.
FG input frequency > fFGLock +6% Overspeed fFGLock 6% Lock range > fFGLock -6% Underspeed Notes fFGLock = Brake Tracking Drive fxtal DIV x 2050 (1025) Operation Lock output High level Low level High level FO output Low level DA output (frequencyvoltage conversion) High level PO output Low level DA output (phasevoltage conversion) High level
(Hz)
Caution: The value in parentheses is used when the FG divider is on.
fFGLock: FG frequency when locked; fxtal: Crystal resonant frequency; DIV: Variable divider ratio
* * * * *
The drive operation is performed at start-up (underspeed) time. When the FO and PO outputs are set to the high level, the motor is driven at full speed. Braking operation is performed when the motor is in overspeed range. When the FO and PO outputs are set to the low level, the motor brake is applied. The servo control block controls the motor by using these two operations to pull the motor speed into the lock range. (Note that the operations described up to this point are the rough adjustments performed by the frequency system.)
(2) FO and PO outputs (frequency system control output and phase system control output) When the FG input frequency enters the lock range, the servo control switches to tracking operation. Frequency system fine control and phase system control starts, and the FO and PO outputs are switched to voltage outputs from internal D/A converters. Since the internal D/A converters are 8-bit converters, these output voltages have 256 possible levels. The figures below show the FO and PO output characteristics. q FO Output Characteristics
q PO Output Characteristics (during tracking)
Caution: These characteristics are for units in the standard comparison range.
No. 4873-8/12
STK6217 3-3 Accessory Functions (1) ROT input (rotate/stop) The ROT input turns the motor on or off.
ROT input High level Low level *: Determined by the motor control function. State Stop Operate FO output Low level * PO output Low level *
(2) PRS1 and PRS2 inputs (phase comparison range selection) The phase system comparison range can be switched using the PRS1 and PRS2 inputs. Phase System Comparison Range Selection
PRS2 input Low level Low level High level High level PRS1 input Low level High level Low level High level Range name Standard range Test mode Double range Quadruple range Comparison range 2 ********* 6 14 Phase output frequency Once every FG input ********************* Once every two FG inputs Once every four FG inputs
Caution: The phase range becomes more than two and four times the normal range due to the operation of a builtin limiter. These phase output frequency values are divided by two when the FG divider is used.
q Phase Output Characteristics
Caution: The "phase difference" is the phase difference in the FG signal input with respect to the internal reference signal. The double and quadruple ranges have hysteresis.
q FG Clock Frequencies (examples)
Variable divider ratio 20 10 6 3 2 ON OFF FG divider Oscillator resonant frequency (MHz) 2.05 50 100 116 333 500 1000 4.1 100 200 333 667 1000 2000 6.15 150 300 500 1000 1500 3000 8.2 200 400 667 1333 2000 4000 10.25 250 500 833 1667 2500 5000 Unit Hz Hz Hz Hz Hz Hz
The following two ceramic oscillators, which are available as commercial products, can be used. CSA6.14MT (Murata) ... Handles FG frequencies of 500, 1000 and 1500 Hz. CSA8.20MT (Murata) ... Handles an FG frequency of 2000 Hz.
No. 4873-9/12
STK6217 4. Rush Current Limiter Circuit 4-1 Circuit Purpose The STK6217 provides a function that can limit the current when the motor starts (or brakes). This function allows the external current (peak) output capacity to be reduced. The rush current limit value can be changed arbitrarily by adjusting the value of an external resistor. 4-2 Setting the Limit Value Figure 3 shows the method for setting the limit value. The Vref voltage is adjusted by changing the value of RO2. Formula 6 is the formula for the limit value, ILIM. ILIM (A) RO2 1 x VCC2 x ............................................................................ } RO1 + RO2 Rs Vref RO1: RO2: VCC2: Rs: 6.8 k (fixed) Variable 5V Current detection resistance ()
Figure 3 External Peripheral Circuit and Motor Start-up Timing Chart Caution: * Here, the Vref voltage must be set in a range that fulfills the following condition. Vref 0.025 V (However, VCC2 = 5 V 5% is the alteration condition.) The limiter function will not operate if the above condition is not met. * Although formula } can be used as a rough formula for setting the output current, the actual value will differ due to the influence of voltage drops due to the ground pattern design external to the hybrid IC. Therefore we recommend that ILIM final confirmation be performed in a circuit that has a form close to that of the PCB final pattern. 4-3 Value of the Current Detection Resistor (Rs) Rs detects current flowing from the motor, and the voltage drop across Rs is sensed by an internal comparator. When an external Rs is connected to the STK6217, a resistor with a value that fulfills the following condition must be used. Rs x ILIM 0.5 V ........................................................................................................... ~ Also, the PCB pattern should be designed so that Rs, RO2 and the STK6217's ground pin (pin 23) are connected to a single ground point as close as possible to the STK6217 in the pattern. In particular, Rs and the STK6217's pins 3 and 4 must not be located any significant distance from the IC.
No. 4873-10/12
STK6217 5. MOSFET Drain-Source Overvoltage When using the STK6217, a diode is connected in parallel with the DC motor as a regenerative diode for the motor. This also functions as a protective measure against excessive MOSFET flyback voltage. Flyback voltage is due to the influence of circuit factors such as lead inductances, and will remain when the MOSFET turns off. (In general, these voltages are a few volts for periods of up to 0.5 s.) Therefore, as a final circuit operation check, confirm that the flyback voltage does not exceed VOSS. 6. Thermal Design Applications must be designed so that the temperature of the STK6217's aluminum substrate side never exceeds 105C in any situation. The remainder of this section discusses thermal design for the STK6217. 6-1 Hybrid IC Average Internal Loss Derivation The main component of the average internal loss occurs in the MOSFET, which is the PWM element. The MOSFET loss is expressed as follows: Pd (W) = VSAT x IM x fp x tON .......................................................................................... VSAT: IM: tO: fp: 6-2 Deriving the heat sink size Formula shows the thermal resistance of the required heat sink.
c-a (C/W) =
FET saturation voltage Motor output peak current FET on time IC internal oscillator frequency
Tc max - Ta ............................................................................................ Pd
A heat sink that is appropriate for c-a must be selected. (Note that c-a for the STK6217 is 18.5C/W.)
No. 4873-11/12
STK6217
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. PS No. 4873-12/12

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